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週四, 23 二月 2012
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VeriSoC

 

Overview


     The SMIMS VeriSoC® is an embedded system with FPGA. It supports software and hardware co-design and co-verification. In the software side, VeriSoC® uses Android OS and provides JAVA API to develop software applications for communicating with the FPGA device. In the hardware side, VeriSoC® uses memory mapping to connect ARM CPU and the FPGA device.

    The above block diagram is the VeriSoC® architecture. There are 16 bits data bus and 6 bits address bus for the communication between FPGA and embedded system.

   The SMIMS VeriSoC® also provides an emulator in a Windows PC and it simulates the embedded system. The emulator connects to the FPGA through the USB port of PC. In the emulator, the same JAVA API used to develop software applications for communicating with the FPGA device.

   

The above block diagram is the VeriSoC® emulator architecture. Based on the USB connection between PC and SMIMS VeriLite device, there is a virtual connection which supports 16 bits data bus and 6 bits address bus for the communication between FPGA and emulator.


Key Features

  • Support Android 1.5 Java development API.
  • Link the Android® SDK emulator with SMIMS® FPGA Platforms in Windows PC.
  • Support FriendlyARM Mini2440 ARM9 board with SMIMS® FPGA Platforms.
  • Support the same Android JAVA application (APK) for emulator and the real hardware (FriendlyARM).
  • Support Eclipse® to develop Android JAVA application.

Specification:

  • SMIMS VeriSoC tools:
    • Android Emulator with SMIMS VeriLite VLXSP6-25: Provide an Android emulator on Windows PC which may co-work with SMIMS FPGA VeriLite VLXSP6-25. development Platform.
    • Android Emulator with SMIMS VeriLite VLAC4-30: Provide an Android emulator on Windows PC which may co-work with SMIMS FPGA VeriLite VLAC4-30. development Platform.
    • VeriSoC Java API: Using Java API to communicate with SMIMS FPGA VeriLite VLXSP6-25/VLAC4-30 development Platform.
    • VeriLite VLXSP6-25 and VLAC4-30 Device Driver: Provide drivers for the different OS of Windows XP/Vista32 on PC, Android 1.5 on Emulator, and Android 1.5 on Mini2440 ARM9 Board.
  • Support 3rd-party development tools:
    • Android SDK: android-sdk_r04-windows with platforms android-1.5
      JDK: version 5 or 6 for windows
    • Eclipse: version 3.4 or 3.5, needed only if you want develop using the ADT Plug-in.
    • Android Development Tools (ADT) : version 0.9.5
    • Android Platforms: version 1.5
    • Xilinx ISE: version 11.1 or later
  • SMIMS VeriLite VLXSP6-25
    • Dimension: 100 x 100 mm
    • FPGA: Xilinx Spartan-6 XC6SLX25
    • FPGA Program: Download FPGA configuration through USB (PC or Mini2440) or JTAG
    • GIO Pin: Up to 36 additional available I/Os with selectable IO Voltages (3.3V or 2.5V)
    • User Outputs: 8 user-defined LEDs
    • User Inputs: 2 user-defined push buttons, 2 user-defined dip switch
    • USB: mini USB x 1, USB 2.0 interface
    • Power: Powered through USB +5V, Power switch
    • LED: 4 indicator LEDs
    • Expansion: Connected to System Bus of Mini2440 ARM9 Board
    • OS Support:
      • Connect to PC: Android Emulator on Windows PC
      • Connect to Mini2440: Android
  • Mini2440 ARM9 Board
  • Verification Software – VeriComm with HDL Ximulation:
         VeriComm is an easy-to-use verification environment which allows easy and quick debugging/analysis for a HDL-based circuit on SMIMS FPGA Platform. HDL Ximulation allows you to view FPGA internal signals or nodes in the Vericomm. A tree view GUI is offered for internal signal selection. With the help of internal signal debugger, the verification time for a user’s circuit can be reduced up to 50%.
    • Input format
      • ASCII Text import
      • Testbench import
      • VCD dump import
      • Waveform editor
      • Audio import from Microphone
      • Video/Image import from Webcam
    • Waveform Display
      • Zoom in/Zoom out/Zoom all
      • Search by edge/value
      • Bookmark
      • Group a bus
    • Output waveform to ASCII Text file
    • HDL Ximulation
      • Up to 1024 internal signals observation
      • RTL level
      • Internal signal selection GUI

 

 

 
 
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